The present invention relates to a process for producing metrological structures particularly useful for analyzing the accuracy of instruments for measuring alignment on processed substrates.
Owing to the ever-increasing complexity in producing integrated circuits in general, which complexity leads to an ever-larger number of devices being produced on the same integrated circuit, a problem which is increasingly encountered by specialists is the alignment among the layers of the device, due to the problems related to the defectiveness or non-defectiveness of the integrated circuit itself.
Commercially available alignment measurement instruments are particularly sensitive to the conditions and physical structure of the markings used, since this fact negatively affects the accuracy and precision of the measurement performed.
In fact, whereas markings defined on a silicon substrate are better defined and sharp, ensuring good measurement accuracy, markings defined in the normal production process on industrially-processed substrates are not as sharp and well-defined, and are thus more difficult to measure.
The markings, or rather profiles, which are defined on a substrate in production are in fact not very distinct and furthermore may have been deteriorated by the various steps of the production process itself.
To the above mentioned problems one must furthermore add that currently there are no standardized absolute metrological references for calibrating the measurement instruments themselves.
Currently, in order to calibrate the measurement instruments used in measuring the alignment of integrated devices, the pitches of known structures on substrates or on appropriate quartz grids, on which chrome reference patterns are defined, are measured.
Unfortunately, the described methods are flawed in that they do not effectively represent the real situations which can occur in the real production process, and therefore they lead to a measurement accuracy which seldom achieves the required sensitivity.